1. Field of the Invention
This invention relates to a novel and improved apparatus and method of phase synchronization useful in a binary data processing apparatus wherein repetitive output signals are synchronized with repetitive input signals applied to the system.
2. Description of the Prior Art
In reading back digital data from, for example, magnetic recording media, a gate is normally triggered by an electronic clock to permit each bit to be read and interpreted properly. The clock signal is normally generated by an oscillator. To ensure correct frequency and phase of the clock signal, it is desirable to lock the oscillator to the data itself by means of a feedback loop. In a phase locking oscillator servosystem, the error detection scheme used in the feedback loop compares the phase of the data signal with that of the oscillator signal. Any difference in phase is used to generate an error signal which is employed to reduce the phase difference. It may be noted that the quantity to be controlled, phase, increases linearly with time, and thus, the input (or command) to the feedback loop is a ramp function.
From basic servo theory, it is known that to follow a ramp input, the feedback loop must contain at least one integration (Type 1 8c system) but that an error (phase misalignment) will exist in the steady state, if such a system is used. A minimum steady-state error requires a high servo gain which however decreases the system's ability to reject "jitter" or "noise.""
Basic servo theory also indicates that if a second integration is cascaded within the feedback loop (Type 2 system), the steady-state error in following the ramp input can be completely eliminated and the noise rejection capability of the system be made now independent of the steady-state error.
Two prior patents showing Type 2 phase locking oscillator servosystems are U.S. Pat. Nos. 3,614,635 (Lapine et al) and 3,701,039 (Lang et al). In the servosystems described therein a signal predicting the time of occurrence of a clock signal characteristic is derived from each received data signal. When the system is synchronized, the prediction signal and the clock signal characteristic should be coincident. The two signals are applied to two channels and one signal is delayed in one channel while the other is delayed in the other channel. In each channel, the delayed and undelayed signals are applied to an AND gate. The outputs of the AND gates are used respectively to operate positive and negative current sources which charge and discharge an integrating network. If data and clock are in phase, both sources are operated for the delay period and two equal and opposite increments of charge, which thus cancel out, are applied to the integrator. If data and clock are not in phase, then the times of operation of the two sources are unequal and an incremental charge is applied to the integrator which represents the phase difference. The overall charge on the integrator is fed back to control the oscillator.
A disadvantage of this kind of system is that the current sources employed may have to operate for very short periods of time, right down to zero pulse width for certain phase differences. Thus high frequency switching circuits are needed. These are expensive and, in fact, are not currently realizable with PNP transistors in integrated circuit form.